Referring to FIG. 1, a circuit for PWM boost switching power supply is shown and comprises: a reference voltage generator 1, an error amplifier 2, an oscillator 3, a sawtooth wave generator 4, a PWM comparator 5, a R-S flip-flop 6, a power MOS switch 7, and a rectifying and filtering circuit consisted of inducer 8, diode 9, capacitor 10, and resistors 11, 12.
The output voltage V0 at startup of the switching power supply is zero, and at this moment the whole loop is not stable. A reference voltage FB-vref generated by the reference voltage generator 1 is transmitted from point D to the terminal “+” of the error amplifier 2, while the terminal “−” of the error amplifier 2 is inputted with the feedback voltage from the division point C of the output voltage V0. Due to the output voltage V0 at startup of the switching power supply is zero, the output of the error amplifier 2 will be high. And then the output of the error amplifier 2 will be inputted to the terminal “−” of PWM comparator 5 so as to be compared with the output of the sawtooth wave generator 4, as shown in FIG. 2.
FIG. 2 shows the waveforms outputted from the oscillator 3, the sawtooth wave generator 4, the PWM comparator 5, and the R-S flip-flop 6 (the waveforms at the points A, E, G, B of FIG. 1), and the output waveform F of the error amplifier 2 is shown in comparison to the output waveform (of point E) outputted from the sawtooth generator 4. When the waveform (at point F) outputted from the error amplifier 2 is higher than the waveform (of point E) outputted from the sawtooth wave generator 4, the voltage outputted from the PWM comparator 5 (of point G) is zero. Once the waveform outputted from the error amplifier 2 is lower than that of the sawtooth generator 4, the PWM comparator 5 will output a square wave. The waveform outputted from the R-S flip-flop 6 (at point B) is opposite to the waveform at point G, and the square wave outputted from the PWM comparator 5 will trigger the terminal “R” of the R-S flip-flop 6 to enable the output voltage of the R-S flip-flop 6 to be zero. When the voltage outputted from the PWM comparator 5 is zero, the oscillator 3 will trigger the terminal “S” of the R-S flip-flop 6, so that the voltage outputted from the R-S flip-flop 6 will be high. The high voltage outputted by the R-S flip-flop 6 will turn on the power MOS switch 7 through point B (as shown in FIG. 1), so as to charge the capacitor 10, and consequently the output voltage V0 will be increased. After the voltage from the division point C of the output voltage V0 (as shown in FIG. 1) is fedback to the error amplifier 2, the output of the error amplifier 2 will be reduced. Despite the reduction of the output of the error amplifier 2, the oscillator 3 will output signals periodically, making the R-S flip-flop 6 generate output pulse, as the arrow indicated in FIG. 2. The output pulse enables the capacitor 6 to be recharged, leading to an overshoot of the output voltage V0, as indicated by the “before-modification line” in FIG. 3. As a result, an inrush current will be caused and will damage the circuit.
The present invention has arisen to mitigate and/or obviate the afore-described disadvantages.